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ASIC Design Verification Engineer

Company: SGS Consulting
Location: San Diego
Posted on: January 17, 2020

Job Description:

Overview: As an ASIC Design Verification Engineer, you will be responsible for verification of digital signal processing hardware designs, specifically data path as well as control intensive digital designs. You will work with the architects of Systems, Hardware designers as well as other SoC team ASIC designers and software engineers to verify designs specific to Digital Sensor subsystems for integration into SoC for mobile applications Minimum Requirements: Bachelor's degree in Science, Engineering, or related field. ASIC design verification UVM-based functional verification, or related work experience. Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology Experienced with Assertions like SVA etc Debug test cases and report verification result to achieve the expected code/functional/line coverage goal; Extensive usage of RTL simulation tools, UVM, System Verilog, Tcl/Perl/Python shell-scripting skills required Preferred Requirements: RTL design verification experience on-chip with custom digital logic. Experience with sensor data processing is a bonus Experience with C/C++/SystemC is a plus. Experience with any of HLS tools: Catapult /Cadence Stratus, SystemC and MATLAB is a plus. Gate level Simulation debug and usage of power extraction tools a plus - provided by Dice

Keywords: SGS Consulting, San Diego , ASIC Design Verification Engineer, Engineering , San Diego, California

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