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RTL Design Engineer

Company: ASICSOFT
Location: Carlsbad
Posted on: January 17, 2020

Job Description:

Position Requirements: Must have 5 years of experience in RTL level ASIC design, including use of a source control system and be able to debug RTL code using simulation tools Prototype lab bring up and silicon validation experience for at least one device Datapath / Packet processing experience DMA/ Datapath design experience PCIE Gen4/ 5 protocol understanding and experience Compression/decompression and encryption/decryption experience is a plus. Must be expert in Verilog, System Verilog and proficient in verification, timing analysis and optimization. Be able to work in Linux and Windows environments Familiarity with Synthesis, STA and Design Audit tools like Spyglass UVM familiarity is desirable Low power design techniques and tool scripting (e.g. Perl) is a plus. - provided by Dice

Keywords: ASICSOFT, San Diego , RTL Design Engineer, Engineering , Carlsbad, California

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