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Principal FPGA Design Engineer

Company: Kyocera
Location: San Diego
Posted on: September 16, 2023

Job Description:

Kyocera International, Inc. has an opening for a Principal FPGA design engineer in San Diego, California.If you have the experience noted below and want to work with an innovative team and great company, apply today! Kyocera International, Inc. is a leading manufacturer of high-tech ceramics, semiconductor components and other products which are used in a variety of industries including aerospace, automotive, industrial and semiconductor.Check out our profile video here!

Check out highlights from how we reward our valued team members and make Kyocera a great team to join!

  • Competitive pay based on experience and an annual bonus program for all employees
  • Flexible work schedules
  • 3 weeks of accrued vacation the first year, higher levels based on years with the company
  • No cap on vacation accruals - employees can cash our or save with no limit
  • Immediate 401(k) eligibility - with company match
  • Pension Program (100% paid by employer)
  • 10 Paid Holidays per year
  • Generous paid "Sick time" for managing the unexpected and caring for your family
  • Medical, Dental and Vision insurance for you and your family with no wait period
  • Life, AD&D and Long-Term Disability Insurance (100% employer paid)
  • Flexible Spending Account (FSA)
  • Paid time off for volunteer activities
  • Employee Assistance Program
  • Tuition reimbursement
  • Adoption Assistance benefit
  • Various wellness benefits including reimbursement for massages and many of our work locations have on-site gyms! With nearly 80,000 employees globally, Kyocera is a leading manufacturer of high-tech Ceramics which are used in a variety of industries including aerospace, automotive, Medical applications, and semiconductor processing. You will find our innovative materials in everything from smart phones to space shuttles!We have a wonderful and robust corporate culture and philosophy based on the experiences and writings of our founder, Dr. Kazuo Inamori, which you can learn more about here! Come find out why we have so many long tenured staff (many with over 30 years of service)!We are not only a great place to work but also a great place to retire from!

    We Love Engineers!

    Job Duties/Responsibilities:
    • Collaborates with System, other FPGA, and firmware engineers for the development of RU.
    • RTL design development, simulation and implementation of the eCPRI interface, uplink, and downlink, PRACH signal processing flows and Xilinx IP primitive.
    • Development of the synchronization plane and management plane function and interface, interface to the embedded ARM cores and radio control software, interface to peripherals such as USB, SPI, I2C, DDR4, and others, and implement OTIC test cases.
    • Primary engineer for the prototype bring-up, debugging, hardware bug tracking, and functional verification.
    • Works proactively with other multi-functional teams to resolve optimum software solutions to improve the quality of the products.
    • Responsible to deliver high quality digital designs for the development of the FPGA design for the radio unit (RU) within a 5G NR Base station. Radio unit is based on the ORAN based split 7-2 architecture using Xilinx Zynq RFSoc for the eCPRI Ethernet interface, and lower physical layer 1 signal processing. It also contains embedded ARM cores and high speed ADC/DACs.
    • Perform any other related duties as required or assigned. REQUIREMENTS/QUALIFICATIONS
      • Bachelor's degree is required, but we highly value Master's or above. Relevant subject areas include Electrical Engineering, Computer Engineering, Computer Science, Math, Physics and other Engineering domains.
      • 7+ years design experience with Xilinx RFSoc or MPSoc.
      • Good interpersonal and organizational skills.
      • Experience crafting RTL for high speed or multiple clock domain designs.
      • Hands-on experience debugging FPGA with integrated logic analyzer (ILA) and oscilloscopes
      • Experience in modem or DSP algorithm developments in FPGAs or ASICs and successfully shipping products based on them.
      • Experience optimizing the segmentation of the design for a target FPGA, synthesizing for FPGA and implementing timing closure.
      • Experience with requirement specifications for PCB design and complex PCB bring up.
      • Familiar with Xilinx IP primitives and their interfaces.
      • Experience with Xilinx Vivado and Petalinux.
      • Experience with processing speed, power consumption optimization, and programmable logic resources optimization.
      • Familiar with cellular system layer 1 signal processing, OFDM waveform, FFT/iFFT, channel filtering, Nyquist sampling, NCO, multi-clock rate decimation/interpolation.
      • Familiar with petalinux and embedded arm core development.
      • Familiar with Ethernet, USB, SPI, I2C communication protocol and physical drivers.
      • Proficiency in the ORAN standards and OTIC test cases is a plus.
      • Proficiency in the 5G NR or LTE wireless communications standards is a plus.
      • Ability to pass background check and drug screen.
      • Eligible to work in ITAR environments.

        Pay rate range: $170,000 - $276,000


        The above statements are intended to describe the work being performed by people assigned to this job. They are not intended to be an exhaustive list of all responsibilities, duties and skills required. The duties and responsibilities of this position are subject to change and other duties may be assigned or removed at any time. This position may require exposure to information subject to US export control regulations, i.e. the International Traffic in Arms Regulation (ITAR) or the Export Administration Regulations (EAR).

        Kyocera International, Inc. values diversity in its workforce, and is proud to be an AAP/EEO employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.

        If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Kyocera International, Inc.'s Human Resources team directly. Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.

Keywords: Kyocera, San Diego , Principal FPGA Design Engineer, Engineering , San Diego, California

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